Verilog-A Compact Model Coding Whitepaper
The Verilog-AMS hardware description language  includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined with some SPICE related specificities are both responsible for the speed and memory consumption differences measured between simulations of Verilog-A compact models in Verilog-A simulators and SPICE simulators. That is the reason why, after presenting these differences, this paper  presents recommendations for developers of Verilog-A compact models who want to optimize their models for SPICE-like simulators and to facilitate the integration of said models into different simulators.
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